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KL5KUSB111
USB to HomePNA General Description
The Kawasaki KL5KUSB111 Controller is a unique single chip solution developed to interface the Universal Serial Bus (USB) to HomePNA-Networks and standard 10base-T Networks. The KL5KUSB111 has been specifically designed to provide a simple solution to communicate with Home Networking Applications at 1 Mb/s and/or 10 Mb/s Ethernet. By utilizing the Kawasaki's USB to Ethernet technology that has been used throughout the industry. The USB controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock generator, HomePNA / Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External Memory Interface and Debug UART. The SIE (Serial Interface Engine) is fully compatible with the USB specification. The Kawasaki USB to HomePNA controller enables the advantages of Home Networking such as Shared Internet access, Printer/peripheral sharing, File and application sharing and Networked gaming.
Features
* * * * * * * Advanced 16 Bit processor for USB transaction processing and control data processing USB interface ver. 1.0/1.1 compliant Integrated Transceivers and SIE (Serial Interface Engine) Internal Clock Generation Utilizes low cost external crystal circuitry 1.5K x 16 Internal RAM buffer Serial Interface for external EEPROM * * * * * * * HomePNA compliant for 1Mb/sec. Fully IEEE 802.3 compliant 10 Mbit/sec Ethernet MAC Layer. Interfaces serially of an external ENDEC PHY. Debug UART External memory interface Compatible with most HomePNA PHY's Watchdog timer 100 pin LQFP package
Block Diagram
Txd Rxd
UART
Timer 0 Timer 1
16 Bit Processor
Watchdog Timer
A15-0
CK DIO
EEPROM Serial Interface
SRAM Interface
16 Bit Address / Data Bus
D15-0 Cntrl.
2 INT 1-0
IRQ
RAM (3KB)
Serial Interface Engine
PLL & Clock Generator
X1 X2
8
1Mb/s PNA and/or 10Mb/s Ethernet
Mask ROM (8KB)
USB Interface
Data Data +
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 2.3
1
KL5KUSB111
USB to HomePNA KL5KUSB111 Application Block Diagram
KL5KUSB111
USB
USB / Ethernet
PHY
Transformer
Serial EEPROM Optional External Memory
Home Network Phy or/and Full duplex 10 Base - T Ethernet
Pin Diagram 100LQFP
VDD XD_15 XD_14 OGND XD_13 XD_12 IGND XD_11 XD_10 XD_9 XD_8 XD_7 XD_6 XD_5 XD_4 XD_3 XD_2 XD_1 XD_0 XA_13 XA_12 XA_11 XA_10 XA_9 XA_8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VDD GND VCO_IN CP_OUT PLLEN N/C N/C N/C N/C N/C N/C VDD GND PHTXD0 PHCOL PHTXEN N/C N/C N/C N/C N/C TXD UGND VP VM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
KL5KUSB111_L
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
XA_7 XA_6 XA_5 XA_4 XA_3 XA_2 XA_1 nTST nRESET nXROMSEL nXWR nXRD GND nPDN N/C N/C N/C N/C LED_ON nXRAMSEL IGND nXBHE XA_0 XA_14 OVDD
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
UVDD N/C N/C PHTCLK PHRXCLK PHCRS PH_RXD0 X_PCLK RXD IRQ0 IRQ1 DXA TSCA FS N/C SERROMD SERROMCLK PU#1 PCLK DRA OGND CLK X2 XA_15 VDD
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Ver. 2.3
2
KL5KUSB111
USB to HomePNA
Pin Description
Pin # LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O IN IN IN OUT IN NC NC NC NC NC NC IN IN OUT IN OUT NC NC NC NC NC IN/OUT IN IN/OUT IN/OUT IN NC NC IN IN IN IN IN/OUT IN/OUT IN IN OUT IN IN/OUT NC IN/OUT OUT IN/OUT Pin Name 0VDD GND VCO_IN CP_OUT PLLEN NC NC NC NC NC NC VDD GND PHTXD0 PHCOL PHTXEN NC NC NC NC NC TXD UGND VP VM UVDD NC NC PHTXCLK PHRXCLK PHCRS PH_RXD0 X_PCLK RXD IRQ0 IRQ1 DXA TSCA FS NC SERROMD SERROMC LK PU#1 Description VDD GND PLL VCO IN PLL VCO OUT PLL Enable NC NC NC NC NC NC VDD GND Transmit data to PHY Collision input from PHY Transmit Enable to PHY NC NC NC NC NC UART TXD USB GND USB+ Pin USB- Pin USB VDD NC NC PHY Transmit Clock PHY Receive Clock PHY Carrier Sense PHY Serial Receive Data External PCLK UART RXD IRQ or GPIO10 IRQ or GPIO11 Sport Mode or GPIO7 Sport Mode or GPIO8 Sport Mode or GPIO9 NC Serial ROM data Serial ROM clk Pull up to USB + Pin for High Speed
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 2.3
3
KL5KUSB111
USB to HomePNA
Pin # LQFP 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 I/O IN IN IN IN OUT OUT IN IN OUT OUT OUT IN OUT IN/OUT NC NC NC NC IN/OUT IN OUT OUT OUT IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT Pin Name PCLK DRA OGND CLK X2 XA_15 VDD 0VDD XA_14 XA_0 nXBHE IGND nXRAMSEL LED_ON NC NC NC NC nPDN GND nXRD nXWR nXROMSEL nRESET nTST XA_1 XA_2 XA_3 XA_4 XA_5 XA_6 XA_7 XA_8 XA_9 XA_10 XA_11 XA_12 XA_13 XD_0 XD_1 XD_2 XD_3 XD_4 XD_5 XD_6 XD_7 XD_8 XD_9 XD_10 Description Sport Mode or GPIO5 Sport Mode or GPIO6 GND 12MHz Clock/Crystal Input 12MHz Crystal Output External Address Pin VDD VDD External Address Pin External Address Pin SRAM Byte High Enable GND SRAM Byte Low Enable Turns on 3.3V to TX LED NC NC NC NC Powerdown to PHY(active LO ) GND External Memory Read (active LO) External Memory Write (active LO) External ROM CS (active LO) Reset Pin Test Pin, NC for Normal Operation External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Data Pin External Data Pin External Data Pin External Data Pin External Data Pin External Data Pin External Data Pin External Data Pin External Data Pin External Data Pin External Data Pin
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 2.3
4
KL5KUSB111
USB to HomePNA
Pin # LQFP 93 94 95 96 97 98 99 100 I/O IN/OUT IN IN/OUT IN/OUT IN IN/OUT IN/OUT IN Pin Name XD_11 IGND XD_12 XD_13 OGND XD_14 XD_15 VDD External Data Pin GND External Data Pin External Data Pin GND External Data Pin External Data Pin VDD Description
Function Description
16 Bit Processor
The integrated 16 bit processor serves as a micro controller for USB peripherals. The processor can execute approximately five million instructions per second. With this processing power it allows the design of intelligent peripherals that can process data prior to passing it on to the host PC, thus improving overall performance of the system. The masked ROM (4K X 16) in the KL5KUSB111 or external memory contains a specialized instruction set that has been designed for highly efficient coding of processing algorithms and USB transaction processing. The 16-bit processor is designed for efficient data execution by having direct access to the RAM Buffer, external memory, I/O interfaces, and all the control and status registers. The divide/multiply feature expands the capability of USB peripherals. The processor supports prioritized vectored hardware interrupts. In addition, as many as 240 software interrupt vectors are available. The processor provides six addressing modes, supporting memory-to-memory, memory-toregister, register-to-register, immediate-to-register or immediate-to-memory operations. Register, direct, immediate, indirect, and indirect indexed addressing modes are supported. In addition, there is an auto-increment mode in which a register, used as an address pointer is automatically incremented after each use, making repetitive operations more efficient both from a programming and a performance standpoint. The processor features a full set of program control, logical, and integer arithmetic instructions. All instructions are sixteen bits wide, although some instructions require operands, which may occupy another one or two words. Several special " short immediate" instructions are available, so that certain frequently used operations with small constant operand will fit into a 16-bit instruction.
The Processor - Divide/Multiply function
The processor's divide/multiply function contains all the instructions of the base processor that additionally includes integer divide and multiply instructions. A signed multiply instruction takes two 16-bit operands and returns a 32-bit result. A signed divide instruction divides a 32-bit operand by a 16-bit operand.
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 2.3
5
KL5KUSB111
USB to HomePNA
RAM Buffer
The USB controller contains a 3K byte (1.5K X 16) internal buffer memory. The memory is used to buffer data and USB packets and accessed by the 16 Bit processor and the SIE. USB transactions are automatically routed to the memory buffer. The 16-bit processor has the ability to set up pointers and block sizes in buffer memory for USB transactions. Data is read from the interface and is processed and packetized by the 16-bit I/O processor.
PLL Clock Generator
The PLL circuitry is provided to generate the internal 48MHz clock requirements. This circuitry is designed to allow use of a low cost 12 MHz external crystal which is connected to the USB3 pins X1 and X2. If an external 12 MHz clock is available in the application, it may be used in lieu of the crystal circuit and connected directly to the X1 input pin.
USB Interface
The USB controller meets the Universal Serial Bus (USB) specification ver 1.0. The transceiver is capable of transmitting and receiving serial data at the USB's full speed, 12 Mbits/sec data rate. The driver portion of the transceiver is differential, while the receive section is comprised of a differential receiver and two single ended receivers. Internally, the transceiver interfaces to the SIE logic. Externally, the transceiver connects to the physical layer of the USB.
1Mb/sec HomePNA Interface
The KL5KUSB111 Controller has a built in 1 Mbit/sec interface to a variety of Home Networking Phys.
10Mb/sec Ethernet Interface
The KL5KUSB111 Controller has a built in 10 Mbit/sec 10-base T Ethernet MAC (Media Access Controller) which is fully compliant with the IEEE 802.3 Ethernet standard. The KL5KUSB111 connects externally to a 10 Base -T ENDEC PHY. The KL5KUSB111 Controller 16-bit processor has direct access to the registers of the MAC.
UART Interface
Supports a transfer rate of 900 to 115.2K baud.
Serial EEPROM Support
The USB Controller serial interface is used to provide access to external EEPROM's. interface can support a variety of serial EEPROM formats. The
SRAM Interface
An address port and 16-bit data port has been provided to interface to an external SRAM.
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 2.3
6
KL5KUSB111
USB to HomePNA
DC CHARACTERISTICS
U2E is implemented with Kawasaki's 0.5um CMOS CBA and Embedded Memory KZ300EM Technology. The followings are the description of chip electric characteristics.
1. Absolute Maximum Ratings
Table 5.1 Absolute Maximum Ratings Parameter Symbol Ratings Supply Voltage Vdd -0.3 ~ 4.0 Input Voltage Vin -0.3 ~ 7.3 DC Output Current Iout 15 Storage Temperature Tstg -55 ~ 125 Unit V V mA C
2. Recommended Operating Conditions
Table 5.2 Recommended Operating Conditions Parameter Symbol Min Typ Operating supply voltage Vdd 3.0 - Operating ambient temperature Ta 0 - Max 3.6 70 Unit V C
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 2.3
7
KL5KUSB111
USB to HomePNA
3. I/O Electrical DC Characteristics (Over Recommended Range)
Table 3.1 DC Characteristics (over recommended range) Parameter Symbol Min Typ Max Unit Test Conditions Input low voltage VIL - - 0.8 V Input high voltage VIH 2.0 - - V Input low current IIL -10 - 10 uA VIN = Gnd Input high current IIH -10 - 10 uA VIN = Vdd Output low voltage VOL - - 0.4 V IOL = 4mA Output high voltage VOH 2.4 - - V IOH = -4mA 3-state leak current IOZ -10 - 10 uA VOH = Gnd or VOL = Vdd Active pull-up current IPU -25 -66 -160 uA VIN = Gnd or VOH = Gnd VIN = Gnd or Vdd Standby current IDDS - 80 100 uA No inputs are cycling. Outputs open. Same conditions as Suspend current ISUSP - 350 450 uA IDDS except for CLKI input buffer 48MHz toggling. IDDOP1 Outputs open. dynamic operating (in busy) - 80 100 mA Vdd = Max. current IDDOP2 FCLKI = FMAX ( (in idle) - 40 50 mA 48MHz ) Input capacitance Output capacitance CIN COUT - - - - 15 15 pF pF Fpin=1MHz, VIN = Gnd. Vin = 100 mVrms
Kawasaki LSI assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice form Kawasaki LSI March 1999 * (c)Copyright 1999 * Kawasaki LSI * Printed in U.S.A
Kawasaki LSI * 2570 North First Street * Suite 301 * San Jose, CA 95131 * Tel: (408) 570-0555 * Fax: (408) 570-0567 * www.klsi.com
Ver. 2.3
8

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